Principle and application of the hottest Bluetooth

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The principle and application of Bluetooth transceiver chip rf2968

1 overview

rf2968 is a monolithic transceiver IC designed for low-cost Bluetooth applications. It has an RF frequency range of 2400 ~ 2500mhz, 79 RF channels, 1MHz step, 1MHz data rate, 140 ~ 175kHz frequency offset, 4dbm output power, 85dBm reception sensitivity, 3V power supply voltage, 59ma transmission consumption current, 49ma reception current and 250 sleep mode current μ A。 The chip provides full-function FSK transceiver function. The if and demodulation parts do not need filters or frequency discriminators. It has image suppression front-end, integrated oscillator circuit, highly programmable synthesis circuit, etc. Automatically calibrated receive and transmit if circuits optimize the performance of the connection and eliminate changes to the. Rf2968 can be used in Bluetooth gsm/gprs/edge cellular, cordless, Bluetooth wireless local area, battery powered portable devices and other systems

2 pin function

the integrated circuit is packaged in the form of 32 pin plastic LCC. The functions of each pin are as follows:

vcc1: supply voltage to VCO (voltage controlled oscillator) frequency doubling and lo (local oscillator) amplifier circuit

vcc2: supply voltage to RX (receive) mixer, txpa (transmit power amplifier) and LNA (low noise amplifier) bias circuit

txout: transmitter output. When the transmitter works, the output impedance of txout is 50 Ω; When the transmitter is not working, txout is in high resistance state. Since this pin is DC biased, an external coupling capacitor is required

rxin: receiver input. When the receiver works,

rxin input impedance is in low resistance state; When the receiver is not working, RXIN is in high resistance state. An internal series inductor is used in the chip to adjust the input impedance

vcc3: supply voltage to RX input stage (LNA)

vcc4: supply voltage to bias circuits of TX mixer, Lo amplifier, LNA and Rx mixer

lpo: low frequency clock output in low power consumption mode. In sleep mode, this pin can provide the baseband with a 3.2khz or 32kHz clock with a duty cycle of 50%. There is no output in other working modes

dvddh: supply voltage to rxifvga circuit

iref: an external precision resistor is connected to generate a constant reference current

vcc5: supply voltage to analog intermediate frequency circuit

d1: This is the charge pump output provided for the clock recovery circuit. Connect an RC network to the ground to determine the bandwidth of the PLL

bpktctl: in the transmission mode, this pin is used as a strobe pulse for starting PA level; In the receiving mode, the baseband controller can selectively use this pin to signal the detection of the synchronization word

bdata1: data output from input signal to transmitter/receiver. The input data is unfiltered data with a rate of 1MHz. This pin is bidirectional and converts to data input or data output according to the transmit and receive modes

recclk: recover clock output

recdata: recover data output

bxtlen: part of the power control circuit, which is used to turn on/key the "sleep" mode of the chip. After the circuit is powered on from the "off" state, when the low-power clock does not work, brclk is controlled by the state of bxtlen (during power on, brclk first writes bxtlen to activate and set it to high level to enter the idle state)

bpclk: reference clock output. This is the reference clock determined by the crystal oscillator. The frequency range is 10 ~ 40MHz, and the typical value is 13mhz. When the circuit is powered on, brclk is activated before the baseband controller sets bxtlen to high level. After the circuit enters the idle state, when the low-power clock does not work, brclk is controlled by the state of bxtlen

osco: same as 19 feet

osci: the OSC pin can generate a reference clock through negative feedback. A parallel crystal oscillator and resistor are connected between soci and osco to provide feedback channel and determine resonance frequency. Each OSC pin is connected with a bypass capacitor to provide appropriate crystal oscillator load. If an external reference frequency is used, it is necessary to connect to osci through a DC isolation capacitor, and connect osco and osci with a 470K Ω resistor

bnden: latch the data input to the serial port. Data is latched on the rising edge of bnden

bddata: serial data channel. Read/write data is input/output to the shift register on the chip through this pin. The read data is transmitted on the rising edge of bdclk, and the write data is transmitted on the falling edge of BDC with low-level supply capacity seriously exceeding LK

bdclk: input clock of serial port. This pin is used to input the clock signal to the serial port. To minimize the programming time of jump frequency, it is recommended to use brclk frequency of 10 ~ 20MHz

bnpwr: part of the chip power control circuit, which is used to control the chip from the "off" state to the power on state

pllgnd: ground terminal of RF synthesizer, crystal oscillator and serial port

vcc6: power supply terminal of RF synthesizer, crystal oscillator and serial port

do:rfpll charging pump output. Connect an RC network to the ground to determine the PLL bandwidth. To minimize the setting time and phase noise of the synthesizer, a dual loop bandwidth scheme can be adopted. At the beginning of frequency detection, 1 wide loop bandwidth is used. At the end of detection frequency, rshunt is used to convert to narrow loop bandwidth and provide improved VCO phase noise. The time of bandwidth conversion is set by the plldel bit

rshunt: the loop filter is converted from narrow band to wide band by shunting the midpoint of two external series resistors to vreg

restr-: used to supply DC voltage to VCO and adjust the center frequency of VCO. Two inductors are required between restr- and restr+ to form resonance with the internal capacitance. The inductive reactance from the restr pin to the inductor should be considered when designing the printed board. A small capacitor can be added between the restr pins to determine the frequency range of the VCO

restr+: see pin 28

vreg: voltage regulation output (2.2V). One bypass capacitor is required to be connected to the ground. The VCO is biased by a circuit connected to pins 28 and 29

ifdgnd: ground terminal of digital intermediate frequency circuit

vcc7: power supply voltage of digital intermediate frequency circuit

3 internal structure

rf2968 is a transceiver designed for Bluetooth applications and operates in the 2.4GHz frequency band. Comply with Bluetooth radio specification version 1.1 power level II (+4dbm) or level III (0dbm). For power level 1 (+20dbm) applications, rf2968 can be used with power amplifier, such as rf2172. The internal block diagram of rf2968 is shown in Figure 1. The chip contains transmitter, receiver, VCO, clock, data bus, chip control logic and other circuits

as the IF filter is integrated in the chip, rf2968 only needs the least external devices, avoiding external devices such as if saw filter and symmetric asymmetric converter. The high resistance state of receiver input and transmit output can eliminate the external receiver/transmitter transfer switch. Rf2968 is connected with antenna, RF bandpass filter and baseband controller to realize a complete Bluetooth solution. In addition to RF signal processing, rf3968 can also complete baseband control, DC compensation, data and clock recovery functions of data modulation

rf2968 transmitter output is internally matched to 50 Ω, and 1 AC coupling capacitor is required. The LNA input of the receiver internally matches the 50 Ω impedance to the front-end filter. The receiver and transmitter are connected with a coupling capacitor between txout and RXIN, sharing a front-end filter. In addition, the transmission channel can be amplified to +20dbm through an external amplifier, and the transmission gain control and received signal strength indication of rf2968 can be connected to make Bluetooth work at power level 1. RSSI data is input through the serial port and provides 1dB resolution when it exceeds the power range of -20 ~ 80dbm. The transmission gain is modulated within 4dB steps and can be set through the serial port

baseband data is sent to the transmitter through bdata1 pin. Bdata1 pin is a bidirectional transmission pin, which is used as the input in the transmit mode and the output in the receive mode. Rf2968 realizes Gaussian filtering of baseband data, FSK modulated if current controlled crystal oscillator (ICO) and if up conversion to RF channel frequency

the frequency generated by the on-chip voltage controlled oscillator (VCO) is half of the local oscillator (LO) frequency, and its special design not only meets the functional requirements of the components, but also multiplies the frequency to the accurate local oscillator frequency. The adjustment range of VCO is set for the two external loop inductors between restr+ and restr-. The voltage is transmitted from the on-chip regulator to VCO, and the regulator is connected between the two loop inductors through a filter network. Due to the need of Bluetooth fast frequency hopping, loop filters (connected to do and rshunt) are particularly important. They determine the hopping and setting time of VCO. Therefore, it is highly recommended to use the component values provided in the circuit diagram

rf2968 can use 10MHz, 11mhz, 12Mhz, 13mhz or 20MHz reference clock frequencies, and can support two times of these frequencies. The clock can be directly sent to osc1 pin by the external reference clock through the DC isolation capacitor. If there is no external reference clock, the reference oscillation circuit can be composed of a crystal oscillator and two capacitors. Whether the reference frequency is generated externally or internally, use a resistor connected between osc1 and osc2 to provide an appropriate offset. The frequency tolerance of the reference frequency must be 20 × Or better, to ensure that the maximum allowable system frequency deviation is kept within the demodulation bandwidth of rf2968. The LPO pin uses a 3.2khz or 32kHz low-power clock to provide a low-frequency clock to the baseband device in the sleep mode. Considering the minimum power consumption of sleep mode and the flexible selection of reference clock frequency, 12Mhz reference clock can be selected

the receiver uses a low if structure to minimize external components. The RF signal is down converted to 1MHz, so that the IF filter can be implanted into the chip. Demodulated data is output at bdata1 pin, and further data processing is completed with baseband PLL data and clock recovery capacitor. D1 is the connecting pin of baseband PLL loop filter. Synchronous data and clock are output at the redata and recclk pins. If the baseband equipment uses rf2968 for clock recovery, the D1 loop filter can be omitted

4 the application

rf2968 RF transceiver acts as the physical layer (PHY) of the Bluetooth system and supports the bluerf (Bluetooth RF) interface between the physical layer and the baseband device

rf2968 has two interfaces with baseband. The serial interface provides the channel for controlling data exchange, and the bidirectional interface provides the channel for modulation and demodulation, timing and chip power control signals. The interface between baseband controller and rf2968 is shown in Figure 2

control data is exchanged between rf2968 and baseband controller through DBUS serial interface protocol. Bdclk, bddata and bnden are signals that conform to the serial interface. The baseband controller is the main control equipment. It starts all the instruments often encountered in rf296 mechanical metrology verification. The allowable error of the indication value of the experimental machine jjg139-1999 verification regulation is generally not more than ± 1%. When the Metrology Department conducts metrology verification, the indication error is mainly reflected in the following ways: 8 register access operation, rf2968 data register can be programmed, or retrieved according to the specific command format and address. Packets are first sent to the MSB. The format of serial data packet is listed in Table 1

Table 1 serial packet format

field bit annotation and operation according to the current relevant good manufacturing practice

device address 3[a7:a5] physical layer is "101"

read/write 1[r/w] "1" is read, "0" is write

register address 5[a4:a0] maximum value of 32 registers

data 16[d15:d0]rf

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